1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device and method of manufacturing a semiconductor device.
2. Description of the Related Art
A power semiconductor device is conventionally known in which a vertical power semiconductor device and a horizontal semiconductor device configuring a control/protection circuit (circuit unit) of the vertical power semiconductor device are disposed on a single semiconductor substrate (semiconductor chip) to increase reliability and reduce size and cost (see, e.g., Japanese Laid-Open Patent Publication Nos. 2002-359294 and 2000-091344). The structure of a conventional semiconductor device will be described taking as an example, a power semiconductor device in which a vertical n-channel power metal-oxide-semiconductor field-effect transistor (MOSFET) for an output stage and a horizontal complementary MOS (CMOS) for a control circuit are disposed on a single semiconductor substrate.
FIG. 25 is a cross-sectional view of a structure of a conventional semiconductor device. The semiconductor device depicted in FIG. 25 is an example of a power semiconductor device in which a vertical MOSFET of trench gate structure is disposed as a vertical n-channel power MOSFET 121 for an output stage. FIG. 25 depicts only a horizontal p-channel MOSFET 122 among the horizontal p-channel MOSFET 122 and a horizontal n-channel MOSFET complementarily connected to configure a horizontal complementary CMOS for a control circuit (similarly in FIGS. 26, 27, 28, and 29). In the vertical n-channel power MOSFET 121, an n−-type semiconductor layer 102 acts as a drift region. In the n−-type semiconductor layer 102, a p-type base region 106 is selectively disposed. In the p-type base region 106, both an n+-type source region 107 and a p+-type diffusion region 108 are selectively disposed.
The p+-type diffusion region 108 is connected to a source electrode 110 through a contact hole 110a that penetrates an interlayer dielectric 109 in a depth direction and reaches the p+-type diffusion region 108, and acts as a contact region electrically connecting the n+-type source region 107 and the source electrode 110. On the other hand, in the horizontal p-channel MOSFET 122 configuring a horizontal CMOS, the n−-type semiconductor layer 102 acts as a base region. In the n−-type semiconductor layer 102, both a p+-type source region 112 and a p+-type drain region 113 are selectively disposed. The p+-type source region 112 and the p+-type drain region 113 are p+-type diffusion regions (source/drain regions (Psd)) that have a relatively high impurity concentration and are formed at respective end portions of the gate electrode 115 in a self-aligning manner by ion implantation using, as a mask, a gate electrode 115 disposed on the n−-type semiconductor layer 102 via a gate insulating film 114.
The p+-type source region 112 is connected to a source electrode 116, which is a metal wiring layer, through a contact hole 116a that penetrates the interlayer dielectric 109 in the depth direction and reaches the p+-type source region 112 to thereby form a source terminal of the horizontal p-channel MOSFET 122. The p+-type drain region 113 is connected to a drain electrode 117, which is a metal wiring layer, through a contact hole 117a that penetrates the interlayer dielectric 109 in the depth direction and reaches the p+-type drain region 113 to thereby form a drain terminal of the horizontal p-channel MOSFET 122. Reference numerals 101, 103 to 105, and 111 denote an n+-type semiconductor layer (drain region), a trench, a gate insulating film, a gate electrode, and a drain electrode, respectively, of the vertical n-channel power MOSFET 121. Reference numeral 120 denotes a local oxidation of silicon (LOCOS) film.
A method of manufacturing the conventional semiconductor device depicted in FIG. 25 will be described. FIGS. 26, 27, 28, and 29 are cross-sectional views of states during manufacturing of the conventional semiconductor device. First, as depicted in FIG. 26, on the front surface side (on the n−-type semiconductor layer 102 side) of a semiconductor wafer formed by stacking the n+-type semiconductor layer 101 and the n−-type semiconductor layer 102, a MOS gate (an insulating gate made of metal oxide film semiconductor) structure that is made up of the p-type base region 106, the n+-type source region 107, the trench 103, the gate insulating film 104, and the gate electrode 105 is formed in a formation region of the vertical n-channel power MOSFET 121. Subsequently, on the front surface of the semiconductor wafer, the gate electrode 115 is formed in a formation region of the horizontal p-channel MOSFET 122, via the gate insulating film 114.
On the front surface of the semiconductor wafer, a resist mask 131 is formed that is open from a portion corresponding to the formation region of the p+-type source region 112 to a portion corresponding to the formation region of the p+-type drain region 113 of the horizontal p-channel MOSFET 122. The resist mask 131 and the gate electrode 115 are used as a mask and ion implantation 132 of a p-type impurity is performed to form the p+-type diffusion regions (Psd) that become the p+-type source region 112 and the p+-type drain region 113 in a self-aligning manner at respective end portions of the gate electrode 115. After the resist mask 131 is removed, the p+-type diffusion regions that become the p+-type source region 112 and the p+-type drain region 113 are diffused by heat treatment.
Subsequently, as depicted in FIG. 27, a resist mask 133 is formed that has an open portion corresponding to the formation region of the p+-type diffusion region 108 of the vertical n-channel power MOSFET 121. By using the resist mask 133 as a mask, ion implantation 134 of a p-type impurity is performed to form the p+-type diffusion region 108 inside the p-type base region 106. After the resist mask 133 is removed, the p+-type diffusion region 108 is diffused by heat treatment. Subsequently, as depicted in FIG. 28, the interlayer dielectric 109 is formed on the front surface of the semiconductor wafer. On the interlayer dielectric 109, a resist mask 135 is formed that has open portions corresponding to formation regions of the contact holes 110a, 116a, and 117a. Reference numeral 135a denotes an open portion of the resist mask 135.
The resist mask 135 is used as a mask and the interlayer dielectric 109 is etched to form the contact holes 110a, 116a, 117a. Subsequently, as depicted in FIG. 29, after the resist mask 135 is removed, a metal wiring layer made of aluminum (Al) is formed to be embedded in the contact holes 110a, 116a, 117a. This metal wiring layer is patterned to leave a portion as the source electrode 110 of the vertical n-channel power MOSFET 121 and portions as the source electrode 116 and the drain electrode 117 of the horizontal p-channel MOSFET 122. On the entire back surface of the semiconductor wafer (the surface on the n+-type drain region side), a back surface electrode 111 is formed as a drain electrode of the vertical n-channel power MOSFET 121. Subsequently, the semiconductor wafer is diced (cut) into individual chip shapes to complete the conventional semiconductor device depicted in FIG. 25.
As a method of manufacturing a single unit of a vertical MOSFET, a method has been proposed that includes performing ion implantation using, as a mask, a contact hole of a MOS transistor to form a high-concentration diffusion region (see, e.g., Japanese Laid-Open Patent Publication No. 2002-057333). As another method of manufacturing a single unit of a vertical MOSFET, the following method has been proposed. In an n−-type epitaxial layer, a p+-type diffusion layer is provided as a back gate region and an n+-type diffusion layer is provided as a drain region. In the p+-type diffusion layer (the back gate region), an n++-diffusion layer is provided as a source region along with a p++-diffusion layer. The p++-diffusion layer is formed by two ion implantation steps according to a shape of a contact hole and has an impurity concentration that is adjusted in a surface portion and a deep portion thereof (see, e.g., Japanese Laid-Open Patent Publication No. 2007-067127).
Nonetheless, there is demand for reductions in the size and cost of a power semiconductor device in which a vertical power semiconductor device and a circuit unit are disposed on a single semiconductor substrate. To meet such demands, studies are being conducted to reduce chip size by reducing the size of the circuit unit (a control/protection circuit of the vertical power semiconductor device) and the vertical power semiconductor device through reduction of ON resistivity (RonA) per unit area; however, the following problem occurs.
If a contact size (a contact area between a metal wiring layer and a p+-type diffusion region) of the horizontal p-channel MOSFET 122 making up a horizontal CMOS for a control circuit is made smaller so as to reduce the size of the circuit unit, this leads to deterioration in contact properties between the metal wiring layer and a semiconductor portion, such as a rise in contact resistivity (i.e., ON resistivity) of the metal wiring layer and the p+-type diffusion region (i.e., the source electrode 116 and the p+-type source region 112, and the drain electrode 117 and the p+-type drain region 113). Therefore, to reduce the size of the circuit unit, measures have to be taken to improve the contact properties between the metal wiring layer and the semiconductor portion of the horizontal p-channel MOSFET 122; however, a problem of increased process cost newly arises.
On the other, if the resist mask 133 is used for forming the p+-type diffusion region 108 as described above, the vertical n-channel power MOSFET 121 has the following problem. FIGS. 30, 31, and 32 are cross-sectional views of a state in which mask displacement occurs during manufacturing of a conventional semiconductor device. As depicted in FIG. 30, if the position of an open portion 133a of the resist mask 133 for forming the p+-type diffusion region 108 is displaced from a predetermined position (in FIG. 30, mask displacement to the right as indicated by a white arrow), the p+-type diffusion region 108 is formed at a position displaced from the predetermined position by an amount corresponding to the amount of displacement of the resist mask 133.
As depicted in FIG. 31, if the position of the open portion 135a of the resist mask 135 for forming the contact hole 110a is displaced in a direction opposite to the displacement direction of the open portion 133a of the resist mask 133 (in FIG. 31, a mask displacement to the left as indicated by a white arrow), the contact hole 110a is formed at position away from the p+-type diffusion region 108. In this state, the p+-type diffusion region 108 may not be exposed in the contact hole 110a depending on the extent of the mask displacement. In this case, as depicted in FIG. 32, the source electrode 110 (metal wiring layer) does not contact the p+-type diffusion region 108 (a portion indicted by reference numeral 141), and the contact properties deteriorate between the metal wiring layer and the semiconductor portion.
Therefore, to make the source electrode 110 and the p+-type diffusion region 108 contact each other, device design has to be performed using device dimensions that ensure margins for displacement of the resist mask 133 for forming the p+-type diffusion region 108 and the resist mask 135 for forming the contact hole 110a. For example, a width of the contact hole 110a (width in the direction of arrangement of the trench 103; hereinafter, simply referred to as the width) must be set to a wide width obtained by adding a margin for mask displacement. However, particularly in vertical MOSFETs of a trench gate structure having a small cell pitch and contact size, ensuring the margins for mask displacement further inhibits reductions in size.